1) Field of the Invention
The present invention relates to a programmable logic circuit apparatus that can be dynamically reconfigured and a programmable logic circuit reconfiguration method. More particularly, the present invention relates to a programmable logic circuit apparatus that can operate processing including branching operating and a programmable logic circuit reconfiguration method that can configure unit circuits including branching processing.
2) Description of the Related Art
As a logic circuit that can be dynamically reconfigured, a Dynamically Programmable Gate Array (DPGA) is known (see Japanese Patent Application Laid-Open No. 2001-202236; Yuichiro SHIBATA et al., “A data driving virtual hardware using an FPGA integrated with DRAM”, Journal of Information Processing Society of Japan, Vol. 40, No. 5, May 1999, pp. 1935–1945; and Xiaoping LING et. al., “WASMII: A multifunction programmable logic device (MPLD) with data driven control”, Journal of the Institute of Electronics, Information and Communication Engineers, D-I, Vol. J77-D-1, No. 4, April 1994, pp. 309–317). The DPGA includes, for example, a plurality of logic blocks which are arranged in a matrix and a plurality of inter-logic-block connectors connecting the blocks. Each logic block provides a comparatively simple logic circuit based on circuit block information and state information which are supplied from an external device.
Specifically, the logic block includes a Look-Up Table (LUT) that can provide a function depending on the circuit block information, and a flip-flop that is initialized by the state information and that holds an output of the LUT.
Each inter-logic-block connector connects between an output of a logic block and an input of a different logic block based on connection information supplied from the external device. In other words, the inter-logic-block connector forms a complicated logic circuit by connecting the logic blocks.
A circuit to be implemented by using the DPGA is previously divided into a plurality of circuit blocks so that the processing by the circuit is performed by the pipeline processing. The DPGA, which merely forms a single circuit block, substantially performs a pipeline processing by reconfiguring the circuit block in an extremely short time, and consequently provides a function of the circuit to be implemented.
However, the conventional DPGA is suitable to provide a circuit including simple sequential processing, and the conventional DPGA does not actively cope with complicated processing such as branch processing which makes the throughput of the whole circuit low by occurrence of frequent circuit block switching.